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1/14 july 2003 n complete interface for two lnbs remote supply and control n guaranteed 400ma output current n lnb selection and stand-by function n built-in tone oscillator factory trimmed at 22khz n fast oscillator start-up facilitates diseqc ? encoding n two supply inputs for lowest dissipation n bypass function for slave operation n lnb short circuit protection and diagnostic n auxiliary modulation input extends flexibility n cable length compensation n internal over temperature protection n backward current protection n cost-effective version of lnbp series description intended for analog and digital satellite receivers, the LNBK20D2 is a monolithic linear voltage regulator, assembled in so-20, specifically designed to provide the powering voltages and the interfacing signals to the lnb downconverter situated in the antenna via the coaxial cable. it has the same functionality of the lnbp1x and lnbp20 series, at a reduced output current capability. since most satellite receivers have two antenna ports, the output voltage of the regulator is available at one of two logic-selectable output pins (lnba, lnbb). when the ic is powered and put in stand-by (en pin low), both regulator outputs are disabled to allow the antenna downconverters to be supplied/controlled by others satellite receivers sharing the same coaxial lines. in this occurrence the device will limit at 3 ma (max) the backward current that could flow from lnba and lnbb output pins to gnd. for slave operation in single dish, dual receiver systems, the bypass function is implemented by an electronic switch between the master input pin (mi) and the lnba pin, thus leaving all lnb powering and control functions to the master receiver. this electronic switch is closed when the device is powered and en pin is low. the regulator outputs can be logic controlled to be 13 or 18 v (typ.) by mean of the vsel pin for remote controlling of lnbs. additionally, it is possible to increment by 1v (typ.) the selected voltage value to compensate the excess voltage drop along the coaxial cable (llc pin high). in order to reduce the power dissipation of the device when the lowest output voltage is selected, the regulator has two supply input pins v cc1 and v cc2 . they must be powered respectively at 16v (min) and 23v (min), and an internal switch automatically will select the suitable supply pin according to the selected output voltage. if adequate heatsink is provided and higher power losses are acceptable, both supply pins can be powered by the same 23v source without affecting any other circuit performance. the ent (tone enable) pin activates the internal oscillator so that the dc output is modulated by a 0.3 v, 22khz (typ.) square wave. this internal oscillator is factory trimmed within a tolerance of 2khz, thus no further adjustments neither external components are required. a burst coding of the 22khz tone can be accomplished thanks to the fast response of the ent input and the prompt oscillator start-up. this helps designers who want to implement the diseqc ? protocols (*). in order to improve design flexibility and to allow implementation of newcoming lnb remote control standards, an analogic modulation input pin is LNBK20D2 lnb supply and control voltage regulator (parallel interface) so-20 .com .com .com
LNBK20D2 2/14 available (extm). an appropriate dc blocking capacitor must be used to couple the modulating signal source to the extm pin. when external modulation is not used, the relevant pin can be left open. two pins are dedicated to the overcurrent protection/monitoring: cext and olf. the overcurrent protection circuit works dynamically: as soon as an overload is detected in either lnb output, the output is shut-down for a time toff determined by the capacitor connected between cext and gnd. simultaneously the olf pin, that is an open collector diagnostic output flag, from high impedance state goes low. after the time has elapsed, the output is resumed for a time t on =1/15t off (typ.) and olf goes in high impedance. if the overload is still present, the protection circuit will cycle again through t off and ton until the overload is removed. typical t on +t off value is 1200ms when a 4.7 m f external capacitor is used. this dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start up even with highly capacitive loads on lnb outputs. the device is packaged in multiwatt15 for thru-holes mounting and in powerso-20 for surface mounting. when a limited functionality in a smaller package matches design needs, a range of cost-effective powerso-10 solutions is also offered. all versions have built-in thermal protection against overheating damage. (*): external components are needed to comply to level 2.x and above (bidirectiona) diseqc ? bus hardware requirements. diseqc ? is a trademark or eutelsat. pin configuration (top view) .com .com .com .com
LNBK20D2 3/14 table a: pin configurations note: the limited pin availability of the powerso-10 package leads to drop some functions. absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these condition is not implied. thermal data pin n symbol name function 1 llc line length compens. (1v typ) logic control input: see truth table 2 olf over load flag logic output (open collector). normally in high impedance, goes low when current or thermal overload occurs 3 mi master input in stand-by mode, the voltage on mi is routed to lnba pin. can be left open if bypass function is not needed 4 lnbb output port see truth tables for voltage and port selection 5, 6, 15, 16 gnd ground circuit ground. it is internally connected to the die frame 7, 13 n.c. not connected 8v cc1 supply input 1 15v to 27v supply. it is automatically selected when v out =13or14v 9v cc2 supply input 2 22v to 27v supply. it is automatically selected when v out =18or19v 10 lnba output port see truth table voltage and port selection. in stand-by mode this port is powered by the mi pin via the internal bypass switch 11 v sel output voltage selection: 13 or 18v (typ) logic control input: see truth table 12 en port enable logic control input: see truth table 14 osel port selection logic control input: see truth table 18 ent 22khz tone enable logic control input: see truth table 19 cext external capacitor timing capacitor used by the dynamic overload protection. typical application is 4.7 m f for a 1200ms cycle 20 extm external modulator external modulation input. needs dc decoupling to the ac source. if not used, can be left open. symbol parameter2 value unit v i dc input voltage (v cc1 ,v cc2 , mi) 28 v i o output current (lnba, lnbb) internally limited ma v i logic input voltage (ent, en osel, vsel, llc) -0.5 to 7 v i sw bypass switch current 900 ma p d power dissipation at t case < 85c 3w t stg storage temperature range -40 to +150 c t op operating junction temperature range -40 to +125 c symbol parameter value unit r thj-case thermal resistance junction-case 15 c/w .com .com .com .com
LNBK20D2 4/14 logic controls truth table note: all logic input pins have internal pull-down resistor (typ. = 250k w ) block diagram control i/o pin name l h out olf i out >i omax or t j >150c i out LNBK20D2 5/14 electrical characteristics for lnbk series (t j = 0 to 85c, c i =0.22 m f, c o =0.1 m f, en=h,ent=l,llc=l,v in1 =16v, v in2 =23v i out =50ma, unless otherwise specified.) symbol parameter test conditions min. typ. max. unit v in1 v cc1 supply voltage i o = 400 ma ent=h, vsel=l, llc=l 15 27 v i o = 400 ma ent=h, vsel=l, llc=h 16 27 v v in2 v cc2 supply voltage i o = 400 ma ent=h, vsel=l, llc=l 22 27 v i o = 400 ma vsel=l, llc=h 23 27 v v o1 output voltage i o = 400 ma vsel=l, llc=l 17.3 18 18.7 v i o = 400 ma ent=h, vsel=l, llc=h 19 v v o2 output voltage i o = 400 ma vsel=l, llc=l 12.5 13 13.5 v i o = 400 ma ent=h, vsel=l, llc=h 14 v d v o line regulation v in1 =15 to 18v v out =13v 5 50 mv v in2 =22 to 25v v out =18v 5 50 mv d v o load regulation v in1 =v in2 =22v v out =13 or 18v i o =0to3a 65 150 mv svr supply voltage rejection v in1 =v in2 =23 0.5v ac f ac = 120 hz, 45 db i max output current limiting 500 650 800 ma t off dynamic overload protection off time output shorted c ext =4.7 m f 1100 ms t on dynamic overload protection on time output shorted c ext =4.7 m ft off /15 ms f tone tone frequency ent=h 20 22 24 khz a tone tone amplitude ent=h 0.55 0.72 0.9 vpp d tone tone duty cycle ent=h 40 50 60 % t r ,t f tone rise and fall time ent=h 5 10 15 m s g extm external modulation gain d v out / d v extm , f = 10hz to 40khz 5 v extm external modulation input voltage ac coupling 400 mvpp z extm external modulation impedance f = 10hz to 40khz 400 w v sw bypass switch voltage drop (mi to lnba) en=l, i sw =300ma, v cc2 -v mi =4v 0.35 0.6 v v ol overload flag pin logic low i ol =8ma 0.28 0.5 v i oz overload flag pin off state leakage current v oh =6v 10 m a v il control input pin logic low 0.8 v v ih control input pin logic high 2.5 v i ih control pins input current v ih =5v 20 m a i cc supply current output disabled (en=l) 0.3 1 ma ent=h, i out =500ma 3.1 6 ma i obk output backward current en=l v lnba =v lnbb = 18v v in1 =v in2 = 22v or floating 0.23ma t shdn temperature shutdown threshold 150 c .com .com .com .com
LNBK20D2 6/14 typical characteristics (unless otherwise specified t j = 25c) figure 1 : output voltage vs output current figure 2 : tone duty cycle vs temperature figure 3 : tone fall time vs temperature figure 4 : tone frequency vs temperature figure 5 : tone rise time vs temperature figure 6 : tone amplitude vs temperature .com .com .com .com
LNBK20D2 7/14 figure 7 : s.v.r. vs frequency figure 8 : external modulation vs temperature figure 9 : bypass switch drop vs output current figure 10 : lnba external modulation gain vs frequency figure 11 : bypass switch drop vs output current figure 12 : overload flag pin logic low vs flag current .com .com .com .com
LNBK20D2 8/14 figure 13 : supply voltage vs temperature figure 14 : supply current vs temperature figure 15 : dynamic overload protection (i sc vs time) figure 16 : tone enable figure 17 : tone disable figure 18 : 22khz tone .com .com .com .com
LNBK20D2 9/14 figure 19 : enable time figure 20 : disable time figure 21 : 18v to 13v change figure 22 : 18v to 13v change typical application schematics two antenna ports receiver ja jb ant connectors 17v 24v mcu+v vcc1 1 vcc2 2 lnba 3 lnbb 15 gnd 8 llc 12 extm 11 osel 7 en 5 ent 9 vsel 4 olf 13 mi 14 cext 10 lnbk20 c2 10uf r1 47k aux data c3 2x 0.1f c1 4.7f c4 c6 c5 2x 47nf ja jb ant connectors 17v 24v mcu+v vcc1 1 vcc2 2 lnba 3 lnbb 15 gnd 8 llc 12 extm 11 osel 7 en 5 ent 9 vsel 4 olf 13 mi 14 cext 10 lnbk20 c2 10uf r1 47k aux data c3 2x 0.1f c1 4.7f c4 c6 c5 2x 47nf tuner i/os mcu i/os vcc tuner i/os mcu i/os vcc + .com .com .com .com
LNBK20D2 10/14 single antenna receiver with master receiver port using serial bus to save mpu i/os 24v 17v mcu+v vcc1 1 vcc2 2 lnba 3 lnbb 15 gnd 8 llc 12 extm 11 osel 7 en 5 ent 9 vsel 4 olf 13 mi 14 cext 10 lnbk20 c2 10uf au x data r1 47k tuner ant master 24v 17v mcu+v vcc1 1 vcc2 2 lnba 3 lnbb 15 gnd 8 llc 12 extm 11 osel 7 en 5 ent 9 vsel 4 olf 13 mi 14 cext 10 lnbk20 c2 10uf au x data r1 47k tuner ant master c4 c5 47nf c3 2x 0.1f c1 4.7f i/os vcc mcu c4 c5 47nf c3 2x 0.1f c1 4.7f i/os vcc mcu i/os + vcc1 1 vcc2 2 lnba 3 lnbb 15 gnd 8 llc 12 extm 11 osel 7 en 5 ent 9 vsel 4 olf 13 mi 14 cext 10 lnbk20 c2 10uf mcu+v r1 47k aux data str 1 d 2 clk 3 oe 15 q1 4 q2 5 q3 6 q4 7 q5 14 q6 13 q7 12 q8 11 qs 9 qs 10 4094 tuner ja jb ant connectors vcc1 1 vcc2 2 lnba 3 lnbb 15 gnd 8 llc 12 extm 11 osel 7 en 5 ent 9 vsel 4 olf 13 mi 14 cext 10 lnbk20 c2 10uf mcu+v r1 47k aux data str 1 d 2 clk 3 oe 15 q1 4 q2 5 q3 6 q4 7 q5 14 q6 13 q7 12 q8 11 qs 9 qs 10 4094 tuner ja jb ant connectors c4 c6 c5 2x 47nf c3 2x 0.1f c1 4.7f mcu+v serial bus c4 c6 c5 2x 47nf c3 2x 0.1f c1 4.7f mcu+v serial bus mcu i/os vcc + 17v mcu i/os vcc + 17v 24v .com .com .com .com
LNBK20D2 11/14 thermal design note during normal operation, this device dissipates some power. at maximum rated output current (400ma), the voltage drop on the linear regulator lead to a total dissipated power that is of about 2w. the heat generated requires a suitable heatsink to keep the junction temperature below the over temperature protection threshold. assuming a 40c temperature inside the set-top-box case, the total rthj-amb has to be less than 43c/w. while this can be easily achieved using a through-hole power package that can be attached to a small heatsink or to the metallic frame of the receiver, a surface mount power package must rely on pcb solutions whose thermal efficiency is often limited. the simplest solution is to use a large, continuous copper area of the gnd layer to dissipate the heat coming from the ic body. the so-20 package of this ic has 4 gnd pins that are not just intended for electrical gnd connection, but also to provide a low thermal resistance path between the silicon chip and the pcb heatsink. given an rthj-c equal to 15c/w, a maximum of 28c/w are left to the pcb heatsink. this figure is achieved if a minimum of 25cm 2 copper area is placed just below the ic body. this area can be the inner gnd layer of a multi-layer pcb, or, in a dual layer pcb, an unbroken gnd area even on the opposite side where the ic is placed. in both cases, the thermal path between the ic gnd pins and the dissipating copper area must exhibit a low thermal resistance. in figure 4, it is shown a suggested layout for the so-20 package with a dual layer pcb, where the ic ground pins and the square dissipating area are thermally connected through 32 vias holes, filled by solder. this arrangement, when l=50mm, achieves an rthc-a of about 28c/w. different layouts are possible, too. basic principles, however, suggest to keep the ic and its ground pins approximately in the middle of the dissipating area; to provide as many vias as possible; to design a dissipating area having a shape as square as possible and not interrupted by other copper traces. so-20 suggested pcb heatsink layout .com .com .com .com
LNBK20D2 12/14 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45? (typ.) d 12.60 13.00 0.496 0.512 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 m 0.75 0.029 s ? (max.) so-20 mechanical data po13l 8 .com .com .com .com
LNBK20D2 13/14 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 30.4 1.197 ao 10.8 11 0.425 0.433 bo 13.2 13.4 0.520 0.528 ko 3.1 3.3 0.122 0.130 po 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 tape & reel so-20 mechanical data .com .com .com .com
LNBK20D2 14/14 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com .com .com .com

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